A 7th Order Unit Element Filter in VIS-SC Technique

ESSCIRC 80: 6th European Solid State Circuits Conference Pub Date : 1980-09-01 DOI:10.1109/ESSCIRC.1980.5468805

D. Herbst, A. Fettweis, B. Hoefflinger, U. Kleine, W. Nientiedt, J. Pandel, R. Schweer

引用次数: 1

Abstract

The large parasitic capacitances of MOS capacitors to substrate usually degrades the performance of VIS-SC filters. It will be discussed, how the effect of such parasitics can be reduced by selection of a suitable set of network elements. Experimental results of a fully integrated 7th order low pass with only 4 op amps will be given.

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VIS-SC技术中的7阶单元元滤波器

MOS电容对衬底的较大寄生电容通常会降低VIS-SC滤波器的性能。我们将讨论如何通过选择一组合适的网络元素来减少这种寄生的影响。本文给出了仅4个运放的全集成7阶低通的实验结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ESSCIRC 80: 6th European Solid State Circuits Conference

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