On Synthesis-for-Testability of Combinational Logic Circuits

Abstract

We propose a synthesis method that modifies a given circuit to reduce the number of gates and the number of paths in the circuit. The synthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for synthesis of testable circuits. Experimental results demonstrate reductions in the number of gates and paths and increased path delay fault testability. The random pattern testability for stuck-at faults remains unchanged.