{"title":"Exploration of an adaptive NoC architecture on FPGA dedicated to multi and hysperspectral algorithm for art authentication","authors":"V. Fresse, Junyan Tan, F. Rousseau","doi":"10.1109/IPTA.2010.5586801","DOIUrl":null,"url":null,"abstract":"This paper presents an adaptive communication architecture dedicated to multispectral and hyperspectral imaging algorithms for art authentication for embedded and portable systems. The communication architecture is a Network on Chip (NoC) architecture implemented on a FPGA (Field Programmable Gate Array). From several parameters extracted from the algorithm, an emulation platform is designed to explore performances of the communication architecture. This emulation architecture contains the NoC architecture associated to generator and receptor traffic blocks to simulate data transfers inside the NoC. Several traffic scenarios extracted from the algorithm are explored. Timing and resource performances are analyzed for several parameterizations of the architecture to identify the adapted architecture and their limitations.","PeriodicalId":236574,"journal":{"name":"2010 2nd International Conference on Image Processing Theory, Tools and Applications","volume":"171 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 2nd International Conference on Image Processing Theory, Tools and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPTA.2010.5586801","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper presents an adaptive communication architecture dedicated to multispectral and hyperspectral imaging algorithms for art authentication for embedded and portable systems. The communication architecture is a Network on Chip (NoC) architecture implemented on a FPGA (Field Programmable Gate Array). From several parameters extracted from the algorithm, an emulation platform is designed to explore performances of the communication architecture. This emulation architecture contains the NoC architecture associated to generator and receptor traffic blocks to simulate data transfers inside the NoC. Several traffic scenarios extracted from the algorithm are explored. Timing and resource performances are analyzed for several parameterizations of the architecture to identify the adapted architecture and their limitations.