{"title":"Modified PPPE architecture for two-dimensional Radon Transform computation","authors":"Baljit Kaur, M. Majumder","doi":"10.1109/ICIIP.2011.6108844","DOIUrl":null,"url":null,"abstract":"In this paper, a modified VLSI architecture for two-dimensional Radon Transform has been presented. The proposed architecture is primarily based on the analytical relationship between the pixels on horizontal and vertical raster scan line and also between the projection angles. The proposed architecture is compared against the existing ‘Parallel Pipeline Projection Engine’ (PPPE) architecture. Implementation of the proposed and PPPE architecture has been done on ‘Field Programmable Gate Array’ (FPGA). It has been observed that the modified architecture reduces the computational complexity, delay and latency as compared to PPPE.","PeriodicalId":201779,"journal":{"name":"2011 International Conference on Image Information Processing","volume":"259 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Conference on Image Information Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIIP.2011.6108844","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, a modified VLSI architecture for two-dimensional Radon Transform has been presented. The proposed architecture is primarily based on the analytical relationship between the pixels on horizontal and vertical raster scan line and also between the projection angles. The proposed architecture is compared against the existing ‘Parallel Pipeline Projection Engine’ (PPPE) architecture. Implementation of the proposed and PPPE architecture has been done on ‘Field Programmable Gate Array’ (FPGA). It has been observed that the modified architecture reduces the computational complexity, delay and latency as compared to PPPE.