{"title":"Design of Bit Width Converter Based on PCIE4.0","authors":"Linjun Liu, Hai Nie, Weiwei Ling","doi":"10.7753/ijcatr1205.1001","DOIUrl":null,"url":null,"abstract":"Aiming at the data bit width conversion module used in PCIE4.0 physical coding layer, this paper designs a backwards compatibility-capable implementation method, which combines the version below backwards compatibility 4.0. According to the data bit width selection signal BusWidth of MAC layer in PCIE protocol, the current running speed of PCIE is selected. So as to select the form of bit width conversion. The designed PCIE internal strobe signal is 32 bits wide, and the correctness of its coding operation mode is verified by using the description language of Verilog hardware and the joint simulation form of Verdi and VCS.","PeriodicalId":104117,"journal":{"name":"International Journal of Computer Applications Technology and Research","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Computer Applications Technology and Research","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.7753/ijcatr1205.1001","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Aiming at the data bit width conversion module used in PCIE4.0 physical coding layer, this paper designs a backwards compatibility-capable implementation method, which combines the version below backwards compatibility 4.0. According to the data bit width selection signal BusWidth of MAC layer in PCIE protocol, the current running speed of PCIE is selected. So as to select the form of bit width conversion. The designed PCIE internal strobe signal is 32 bits wide, and the correctness of its coding operation mode is verified by using the description language of Verilog hardware and the joint simulation form of Verdi and VCS.