Evaluation of RISC-V Silicon Under Neutron Radiation

Michael J. Cannizzaro, Alan D. George
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引用次数: 2

Abstract

Radiation-hardened (rad-hard) components are frequently used in reliable spacecraft-computing systems. While these components improve mission dependability, they also suffer from high development and integration costs, support relatively low operating frequencies, and leverage outdated architectures. These characteristics motivate the consideration of more cost-effective and performant commercial alternatives. The open-source and highly configurable RISC-V architecture has recently become a popular choice for both space and commercial applications. While the reliability of RISC-V on FPGAs has been evaluated extensively, commercial RISC-V silicon has only begun to be investigated in a similar manner. This study evaluates the single-event upset (SEU) susceptibility of two commercial RISC-V processors, the Microchip PolarFire SoC and the SiFive HiFive Unmatched, in the presence of neutron radiation. These devices are compared to the flight-proven Xilinx Zynq-7020 system-on-chip, which contains an ARM Cortex-A9 processor. The industry-standard EEMBC CoreMark and SHREC-developed SpaceBench benchmarks are used to evaluate the presence of data and execution errors on each device under test (DUT). Neutron radiation beam testing was performed at the Los Alamos Neutron Science Center (LANSCE) Weapons Neutron Research (WNR) facility. Data- and execution-error results were recorded and analyzed to measure the proportion of errors present out of all calculations performed during the experiment. Effective dosimetry was also used to calculate cross sections of the processors that are susceptible to SEUs. The Po-larFire and Unmatched DUTs experienced no errors in 99.70% and 99.59% of operations, respectively. The Zynq achieved only 65.23% error-free operations. Execution errors were observed in 0.28%, 0.38%, and 18.67% of operations performed by the PolarFire, Unmatched, and Zynq, respectively. Similar trends were seen for data errors, with the PolarFire, Unmatched, and Zynq experiencing data errors in 0.02%, 0.03%, and 16.10% of operations, respectively. These results alongside dosimetry data produced cross sections of 8.033 × 10–12cm2 for the PolarFire and 8.342 × 10–12 cm2 for the Unmatched, indicating the area vulnerable to SEUs. The calculated cross section for the Cortex-A9 in the Zynq-7020 was 3.759 × 10–9 cm2a much larger value compared to either RISC-V platform. Both the error and cross-section analyses suggest that the evaluated commercial RISC-V devices have significantly lower SEU sus-ceptibility compared to the flight-proven Cortex-A9 platform, showing great promise for the reliable use of RISC-V silicon in embedded space applications.
RISC-V硅在中子辐射下的性能评价
抗辐射(抗辐射)组件经常用于可靠的航天器计算系统。虽然这些组件提高了任务的可靠性,但它们也受到高开发和集成成本的影响,支持相对较低的操作频率,并利用过时的架构。这些特点促使人们考虑更具成本效益和性能的商业替代品。开源和高度可配置的RISC-V架构最近已成为空间和商业应用的热门选择。虽然RISC-V在fpga上的可靠性已经得到了广泛的评估,但商用RISC-V芯片才刚刚开始以类似的方式进行研究。本研究评估了两种商用RISC-V处理器(Microchip PolarFire SoC和SiFive HiFive Unmatched)在中子辐射存在下的单事件扰动(SEU)敏感性。这些设备与经过飞行验证的Xilinx Zynq-7020片上系统进行了比较,后者包含一个ARM Cortex-A9处理器。行业标准EEMBC CoreMark和shrec开发的SpaceBench基准测试用于评估每个被测设备(DUT)上数据和执行错误的存在。中子辐射束测试在洛斯阿拉莫斯中子科学中心(LANSCE)武器中子研究(WNR)设施进行。记录和分析数据和执行错误的结果,以测量在实验期间执行的所有计算中出现的错误的比例。有效剂量法还用于计算易受SEUs影响的处理器的横截面。Po-larFire和Unmatched dut分别在99.70%和99.59%的操作中没有错误。Zynq只有65.23%的操作是无错误的。在PolarFire、Unmatched和Zynq执行的操作中,执行错误分别为0.28%、0.38%和18.67%。数据错误也出现了类似的趋势,PolarFire、Unmatched和Zynq的数据错误率分别为0.02%、0.03%和16.10%。这些结果与剂量学数据一起显示,polpolfire的横截面为8.033 × 10-12cm2, Unmatched的横截面为8.342 × 10-12 cm2,表明该区域容易受到seu的影响。Zynq-7020中Cortex-A9的计算截面为3.759 × 10-9 cm2a,比任何RISC-V平台都要大得多。误差和截面分析都表明,与经过飞行验证的Cortex-A9平台相比,评估的商用RISC-V器件的SEU敏感性显着降低,这表明RISC-V芯片在嵌入式空间应用中的可靠使用前景广阔。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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