Implementation of Ultra Low-Power 8 Bit CLA Using Single Phase Adiabatic Dynamic Logic

Abstract

The paper presents the implementation of ultra low power 8 bit carry look ahead adder circuit operated by single-phase adiabatic dynamic logic (SPADL) which, unlike any other existing adiabatic logic family, uses single sinusoidal supply-clock. This not only ensures higher energy efficiency, but also simplifies the clock design which would be otherwise more complicated due to the signal synchronization requirement. Static logic resembled characteristics of SPADL logic substantially decreases circuit complexity with improved driving ability and circuit robustness. in TSMC 0.18μm CMOS technology. CADENCE simulations show that SPADL saves 65% to 50% and 30% to 40% of total energy compared to Conventional CMOS and other existing single phase adiabatic logic based CLA for a frequency of 1MHz to 100MHz.