A DC-10.5-GHz CMOS Distributed Amplifier with 3.2±0.3 dB NF, 10.5±1.4 dB Gain and ±13.8 ps Group Delay Variation

Abstract

A DC-10.5-GHz CMOS distributed amplifier (DA) with flat and low noise figure (NF), flat and high power gain (S21), and small group delay variation using standard 0.18 µm CMOS technology is demonstrated. Flat and low NF was achieved by adopting the proposed RLC terminal network with 140 Ω terminal resistance at dc and very high frequencies (instead of the traditional 50 Ω terminal resistance or the recently proposed RL terminal network) for the gate transmission line, and a slightly under-damped Q-factor for the second-order NF frequency response. Besides, flat and high S21 was achieved by using cascoded transistors as the gain cell. Over the DC-10.5-GHz band, the DA consumed 29.16 mW and achieved flat and high S21 of 10.5±1.4 dB, flat and low NF of 3.2±0.3 dB, and excellent phase linearity (the group delay variation was only ±13.8 ps), one of the best NF and phase linearity results ever reported for a CMOS DA or wideband LNA with bandwidth greater 7.5 GHz.