Sorting networks with built-in error correction

Abstract

A sorting network with built-in error correction is proposed in this paper. A time shared TMR scheme is used to achieve the error correcting capability. A quarter of the original sorting network based on perfect shuffle is triplicated and voted in each stage. The hardware complexity of this time shared TMR error correcting sorting network is a little more than the original sorting network. The price is that the delay time increases by a factor of 4. However, the throughput penalty can be minimized by pipelining. A technology-independent gate level analysis of hardware complexity and delay time is included in this paper. Possible variations of the basic design are also discussed.