Some practical issues in the design of fault-tolerant multiprocessors

Abstract

A node-covering approach to fault-tolerant design is generalized to apply to a wide class of multiprocessor structures whose structure and failure mechanisms are represented by arbitrary graphs. Several new types of covering graphs are defined, which lead to various design tradeoffs. A new technique for incremental design, using a class of switch implementations that reduce a system's interconnection costs, is presented. The reduction of other cost factors is addressed, including VLSI layout area minimization, efficient transfer of state information during recovery, and the efficient use of local spares. A fast and distributed algorithm for reconfiguration around faults is presented. A review of the general node covering theory is included, focusing on how it models the important practical features of fault-tolerant systems.<>