Hierarchical Network Partitioning for Reconfigurable Large-Scale Neuromorphic Systems

Abstract

We present an efficient and scalable partitioning method for mapping large-scale neural network models to reconfigurable neuromorphic hardware. The partitioning framework is optimized for compute-balanced, memory -efficient parallel processing targeting low-latency execution and dense synaptic storage, with minimal routing across various compute cores. We demonstrate highly scalable and efficient partitioning for connectivity-aware and hierarchical address-event routing resource-optimized mapping, significantly reducing the total communication volume recursively when compared to random balanced assignment. We evaluate the partitioning algorithm on synthetic small-world networks with varying degrees of sparsity factor and fan-out. The combination of our method and practical results suggest a promising path towards extending to very large-scale networks and more degrees of hierarchy.