On the Implementation of Vertical Shuffle Scheduling Decoder for Joint MIMO Detection and Channel Decoding System

Abstract

This paper presents a novel architecture of a soft NB-LDPC decoder for joint iterative MIMO receivers. The architecture is able to decode the rate R= 1/2 with frame length N=384 LDPC code using a 64 QAM modulation. To our knowledge, it is the first soft decoder architecture that implements the belief propagation algorithm based on vertical shuffle schedule. The proposed architecture implements a single variable node processor where the Log Likelihood Ratio (LLR) computation block is removed. It also implements a single Check Node processor that is composed of six Elementary Check Nodes. Synthesis results show that the proposed architecture consumes 6.476 K slices and run at a maximum clock frequency of 70 MHz. Taking only the decoding process part alone, 188 clock cycles are required to perform decoding iterations.