An Alternative Cyclic Synchronous Mirror Delay for Versatility in Highly Integrated SoC

Abstract

We describe an alternative cyclic synchronous mirror delay (ACSMD) for highly integrated SoCs of mobile application processors. ACSMD provides the following advantages: wide operational frequency range from 0.5 to 400 MHz, 0.08 mm2 chip area, and 6.13 mW power consumption @ 400 MHz operation. The chip area and power consumption are reduced by 95% of those of a conventional hierarchical SMD with the same operational frequency and resolution. Key circuit technologies are cyclic delay line, alternating use of three delay lines, and a new loop counter.