Loop regularization for image and video processing on instruction level parallel architectures

Abstract

This paper presents a novel loop transformation (Loop Regularization, LR) that increases the execution efficiency of image and video processing programs running on instruction level parallel (ILP) processors. LR is specifically, devised for those ILP processors that do not include hardware mechanisms for instruction reordering and register renaming such as today's low cost processors for embedded systems and digital signal processors. This paper shows the effects of LR and reports on a set of system-level experiments that validate the technique.