A framework for macro- and micro-time to model VHDL attributes

Abstract

The work presented introduces a formal definition of some important constructs of VHDL, using a formally defined language. Both macro time and micro time scales are used. The inclusion of micro time, or time deltas, allows the authors to describe variables as well as signals. For the purpose of illustration they present the signal attributes of VHDL. This work represents a prelude to the complete translation of VHDL into the formal verification language SIGNAL. SIGNAL can then provide a basis for verifying VHDL programs.<>