Radiation damage characterization of digital integrated circuits

S. Sondon, P. Mandolesi, P. Julián, F. Palumbo, M. Alurralde, A. Filevich
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引用次数: 1

Abstract

A set of gates and registers was fabricated on a submicron CMOS process using radiation hardening by design techniques. The circuits were irradiated in a TANDEM accelerator with 10 MeV protons on three different doses. Off-line characterization of devices was carried out. Measurements showed minimum shifts on the electrical parameters of transistors. Noise margins and gain of combinational logic gates were unchanged and no increase on leakage current was observed. This work suggests that considerable tolerance to this kind of radiation damage can be reached when accurate design techniques are used together with modern integrated circuits technologies.
数字集成电路的辐射损伤特性
采用辐射硬化设计技术,在亚微米CMOS工艺上制备了一组栅极和寄存器。这些电路在TANDEM加速器中以三种不同剂量的10 MeV质子照射。对器件进行了离线表征。测量结果显示晶体管的电学参数变化最小。组合逻辑门的噪声裕度和增益不变,漏电流没有增加。这项工作表明,当精确的设计技术与现代集成电路技术结合使用时,可以达到对这种辐射损伤的相当大的容忍度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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