Experimental Investigation on Failure Mechanism of SiC Power MOSFETs under Single Pulse Avalanche Stress

Abstract

In this paper, the typical V-T (avalanche voltage v.s. temperature) model is used to estimate the maximum junction temperature (Tj) during the single pulse unclamped inductive switching (UIS) tests. Experimental results show that the maximum Tj at failure will reach 670$\sim$890K, which is less than the melting point of aluminum (933K). The typical parasitic BJT turn-on model with practical chip layout is used to analyze the possible failure mechanism. Different Tj calculation models are compared to show the accuracy of the V-T model. The UIS tests at different ambient temperatures are conducted to show the device failure is independent on the fixed critical temperature. Distribution of failure spots of decapsulated failed DUTs is observed under the optical microscope.