Feasibility conditions on PID controller synthesis using dominant pole assignment

Abstract

This paper presents a method for PID controller design which can achieve dominant pole assignment using two of the controller parameters. The non-dominant poles are restricted on the left of the line s = σ̂, where σ̂ is the minimum feasible value, called as the feasibility border. It is obvious that a dominant pole assignment is not practical if σ̂ is close to the real parts of the required dominant poles. Hence, finding σ̂ for a given system is very important. The method, which parameterizes all such controllers in order to allow further design criteria, can be applied to other kinds of low-order compensators.