Thermal distribution and reliability prediction for 3D Networks-on-Chip

K. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran
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引用次数: 1

Abstract

As one of the most promising technologies to reduce footprint, power consumption and wire latency, Three Dimensional Integrated Circuits (3D-ICs) is considered as the near future for VLSI system. Combining with the Network-on-Chip infrastructure to obtain 3D Networks-on-Chip (3D-NoCs), the new on-chip communication paradigm brings several advantages. However, thermal dissipation is one of the most critical challenges for 3D-ICs, where the heat cannot easily transfer through several layers of silicon. Consequently, the high-temperature area also confronts the reliability threat as the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature as in Black’s model. Apparently, 3D-NoCs and 3D ICs must tackle this fundamental problem in order to be widely used. However, the thermal analyses usually require complicated simulation and might cost an enormous execution time. As a closed-loop design flow, designers may take several times to optimize their designs which significantly increase the thermal analyzing time. Furthermore, reliability prediction also requires both completed design and thermal prediction, and designer can use the result as a feedback for their optimization. As we can observe two big gaps in the design flow, it is difficult to obtain both of them which put 3D-NoCs under thermal throttling and reliability threats. Therefore, in this work, we investigate the thermal distribution and reliability prediction of 3D-NoCs. We first present a new method to help simulate the temperature (both steady and transient) using traffic values from realistic and synthetic benchmarks and the power consumption from standard VLSI design flow. Then, based on the proposed method, we further predict the relative reliability between different parts of the network. Experimental results show that the method has an extremely fast execution time in comparison to the acceleration lifetime test. Furthermore, we compare the thermal behavior and reliability between Monolithic design and TSV-based design.  We also explore the ability to implement the thermal via a mechanism to help reduce the operating temperature.
三维片上网络的热分布与可靠性预测
三维集成电路(3d - ic)被认为是VLSI系统的未来发展方向之一,是最有前途的技术之一,可以减少占地面积、功耗和布线延迟。与片上网络基础设施相结合,获得3D片上网络(3D- noc),新的片上通信范式带来了几个优势。然而,散热是3d - ic最关键的挑战之一,热量不能轻易地通过几层硅传递。因此,在black模型中,高温区域也面临可靠性威胁,因为平均故障时间(MTTF)随工作温度呈指数下降。显然,3D- noc和3D ic必须解决这个基本问题才能得到广泛应用。然而,热分析通常需要复杂的模拟,并且可能花费大量的执行时间。作为一个闭环设计流程,设计人员可能需要多次优化他们的设计,这大大增加了热分析时间。此外,可靠性预测还需要完成设计和热预测,设计人员可以将结果作为优化的反馈。由于设计流程中存在两个较大的缺口,因此很难同时获得这两个缺口,这使得3d - noc面临热节流和可靠性威胁。因此,在这项工作中,我们研究了3d - noc的热分布和可靠性预测。我们首先提出了一种新的方法来帮助模拟温度(稳定和瞬态),使用来自现实和合成基准的流量值以及来自标准VLSI设计流程的功耗。然后,在此基础上,进一步预测网络各部分之间的相对可靠性。实验结果表明,与加速寿命测试相比,该方法具有极快的执行时间。此外,我们还比较了单片设计和基于tsv的设计的热性能和可靠性。我们还探索了通过一种机制来实现热的能力,以帮助降低工作温度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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