{"title":"Throughput Improvement of an Autocorrelation Block for Time Synchronization in OFDM-based LiFi","authors":"Erwin Setiawan, T. Adiono","doi":"10.1109/ISOCC47750.2019.9078499","DOIUrl":null,"url":null,"abstract":"In this paper, the throughput improvement of an autocorrelation block is presented. The improvement is carried out by employing pipeline architecture. The autocorrelation block is used for time synchronization in OFDM-based Visible Light Communication (VLC) system. The autocorrelation block estimates the coarse time offset of the received OFDM data symbol. By adding pipeline registers, we can reduce the critical path of the combinational circuits by dividing it into smaller critical path, therefore the clock frequency can be increased. We show three times throughput improvement by using four stages pipeline architecture. The maximum clock frequency of the block is 188 MHz. The block has been implemented and verified on Xilinx Zynq-7000 FPGA.","PeriodicalId":113802,"journal":{"name":"2019 International SoC Design Conference (ISOCC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC47750.2019.9078499","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, the throughput improvement of an autocorrelation block is presented. The improvement is carried out by employing pipeline architecture. The autocorrelation block is used for time synchronization in OFDM-based Visible Light Communication (VLC) system. The autocorrelation block estimates the coarse time offset of the received OFDM data symbol. By adding pipeline registers, we can reduce the critical path of the combinational circuits by dividing it into smaller critical path, therefore the clock frequency can be increased. We show three times throughput improvement by using four stages pipeline architecture. The maximum clock frequency of the block is 188 MHz. The block has been implemented and verified on Xilinx Zynq-7000 FPGA.