Analysis and design of low-voltage CMOS current memory cells using switched current techniques

Abstract

This paper presents a detailed temporal analysis of two-step switched current (S/sup 2/I) memory cells. Also, a new design of an SI current copier operating with a single 1V supply is presented. The analysis and design are supported and validated by SPICE simulations using 0.25 /spl mu/m CMOS process parameters.