A Modified Partially Parallel Polar Encoder Architecture

Abstract

Polar codes are highly channel efficient with minimum hardware complexity with increasing code length, making them one of the most favorable error-correcting codes. There exist many architectures for both encoding and decoding of polar codes. In this paper a modified partially parallel polar encoder architecture is proposed. The registers that are used for inducing the parallelism in the architecture are replaced with pulsed latches, making the whole architecture low power and area efficient. The synthesis and simulation of the proposed architecture is carried out in Xilinx ISE for (16,k), (32,k) and (64,k) polar codes. Results show that the proposed architecture leads to an average reduction of 50% and 45% in power and gate count respectively.