Uncommitted logic array which provides cost-effective multiplication even for long words

Abstract

Large-scale integration has permitted the design of 4×4, 8×8 and even 16×16 multiplier systems on a single chip. This paper discusses methods of multiplication and identifies a method which is particularly suited to bit-slice integration and the multiplication of longer words such as 64 × 64 bits. A 2-bit slice has been designed on an uncommitted logic array, and these have been built into and tested in a 16 × 16 bit system. The results of the experiment are reported, and extrapolation from these show that a 64 × 64 bit multiplier can be built with 71 integrated-circuit chips to provide a multiplication time of less than 290 ns. Other developments are indicated which show that a reduction of these figures to 56 chips and 115 ns can be achieved. An alternative design using the same u.l.a. is found to be more expensive at 128 chips, but enables the time to be reduced to 80 ns. A number of other multipliers are also discussed, several of which would be an economical proposition as a high-performance add-on unit for many mini- and microcomputers. However, the u.l.a. design proposed here is found to be the most cost-effective system.