Area Efficient Low-Power Static Explicit-Pulsed Flip-Flop with Local Feedback

Abstract

In this paper, a static explicit-pulsed single/double edge-triggered flip-flop suitable for low-power application is presented. It offers energy savings by reduction unnecessary internal switching activities. All circuits are simulated in 0.18-μm CMOS technology with a supply voltage of 1.8V. The developed circuit provides up to 18.1% total gate-area reduction and also 19.4% improvement in the power-delay over the best performing flip-flop reported to-date.