Design guidelines for soft implementations to embedded NoCs of FPGAs

Abstract

To overcome point-to-point interconnect obstacles, Networks-on-Chips (NoCs) within FPGAs have been introduced. NoCs provide independent interfaces of communication which lead to increasing design scalability and improving its efficiency. We analyze area, delay and power gaps between soft and hard implementations on FPGA-specific NoC; and target two different configurations in soft implementation. The first configuration targets reducing the delay gap by a factor of 5.5é between soft and hard implementations at the expense of increasing the power gap to be a factor of 12.2×. The second configuration is more suitable for applications that are concerned with power saving. It reduces the power gap to a factor of 4.5× with a small increase in the delay gab by a factor of 6.3× and the area gap is increased from 5.9× to 6.9×.