Processor-Time Tradeoffs for Cayley Graph Interconnection Networks

Abstract

We show that every processor array whose interconnection network is based on a Cayley graph of nonso that the graph's underlying group has a nontrivia size \ subgroup) can be emulated in a workpreserving manner, on general computations, by a (smaller) quotient array. If the underlying group has nontrivial snbgroups of several orders, one thus can choose among several matchups of time and hardware requirements. Our emulations gain efficiency when additional structural uniformity is present.