Layered Spiral Algorithm for memory-aware mapping and scheduling on Network-on-Chip

Abstract

In this paper, Layered Spiral Algorithm (LSA) is proposed for memory-aware application mapping and scheduling onto Network-on-Chip (NoC) based Multi-Processor System-on-Chip (MPSoC). The energy consumption is optimized while keeping high task level parallelism. The experimental evaluation indicates that if memory-awareness is not considered during mapping and scheduling, memory overflows may occur. The underlying problem is also modeled as a Mixed Integer Linear Programming (MILP) problem and solved using an efficient branch-and-bound algorithm to compare optimal solutions with results achieved by LSA. Comparing to MILP solutions, the LSA results demonstrate only about 20% and 12% increase of total communication cost in case of a small and middle size synthetic problem, respectively, while it is order of magnitude faster than the MILP solutions. Therefore, the LSA can find acceptable total communication cost with a low runtime complexity, enabling quick exploration of large design spaces, which is infeasible for exhaustive search.