VLSI implementation of a 256*256 crossbar interconnection network

Abstract

Despite the fact that a crossbar interconnection network is desirable in parallel processing systems due to its flexibility of configuration and simplicity of control, many of the crossbars developed up to this time are small in size. The paper presents the analysis of VLSI layout size and signal delay of the previous crossbar circuits. Also a circuit with better layout size and signal delay is presented in comparison. Based on the new circuit, the feasibility of the implementation is shown for a 256*256 crossbar on a 1cm/sup 2/ CMOS VLSI chip.<>