Design methodology for a CMOS based power amplifier deploying a passive inductor

M. Božanić, S. Sinha
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引用次数: 4

Abstract

This paper presents the design methodology of an integrated power amplifier (PA), and coins the methodology as a software routine: for a given set of PA specifications, CMOS process parameters, the routine computes the passive component values for a Class-E based PA. The routine includes the matching network for standard impedance loads. The program also provides its user with a spiral inductor calculator, which can be used to determine inductance and parasitic values for an integrated square planar spiral inductor. The same tool has the ability to extract SPICE (tSPICE) netlist of inductor geometry, which can be used in the post-layout simulations of the PA. Operation of the program was demonstrated by simulations in AMS 0.35 mum single-supply process for a 10 dBm, 2.4 GHz PA design.
采用无源电感的CMOS功率放大器的设计方法
本文介绍了集成功率放大器(PA)的设计方法,并将该方法作为软件例程:对于给定的PA规格,CMOS工艺参数,例程计算基于e类PA的无源元件值。该程序包括标准阻抗负载的匹配网络。该程序还为用户提供了一个螺旋电感计算器,可用于确定集成方形平面螺旋电感的电感和寄生值。该工具还具有提取电感几何形状的SPICE (tSPICE)网表的能力,可用于放大器的布局后仿真。在ams0.35 μ m单电源工艺中,对10dbm 2.4 GHz PA设计进行了仿真验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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