Finite state machines: a deeper look into synthesis optimization for VHDL

Abstract

This paper provides a deeper insight into the synthesis mechanism of VHDL tools. It examines three methods of writing VHDL code, and each of the three models finite state machines in a different way. There can be significant reductions in the VLSI area and improvements in performance by adopting a certain modeling style, but this is at the cost of writing low level VHDL code, thereby undermining the purpose of VHDL as the design, entry medium. However, there is a simpler approach, which is demonstrated by a software tool called vtvt which allows writing VHDL code at high level and optimizes for area and performance without the burden of writing and maintaining low level code.