SoC-FPGA-Based Implementation of Iris Recognition Enhanced by QC-LDPC Codes

Abstract

Introducing error correction codes into an iris recognition system to solve the intrinsic fuzziness, like variability and noise in iris codes is a research area that hasn't catch massive attention, but the positive effect brought by error correction should not be underestimated. Rather than theoretical analysis and simulation that have been well-understood and deeply explored, in this paper, we focus on an iris recognition system implementation with an error correction scheme, namely QC-LDPC and the whole system is based on a compact SoCFPGA platform which is a DE-10 nano Cyclone V SOC evaluation board by Intel. Every iris information bit as the input data in this platform will be stored after they are encoded as QC-LDPC codes which make the whole system more feasible than normal LDPC codes and loaded to improve the acceptance rate when a verification request is invoked with a new series of iris information. Moreover, the fundamental modules, such as iris processing, LDPC encoding and decoding in the system are reorganized and distributed to which section (HPS or FPGA) they are more suitable to be employed into, leading to a single chip design.