{"title":"The Multi-Protocol Gigabit-Per-Second Isochronet Switch Design And Implementation","authors":"D. Florissi, Y. Yemini","doi":"10.1109/HPCS.1995.662032","DOIUrl":null,"url":null,"abstract":"This paper overviews rhe elecrronic design and implementation of a switch based on the Isochronets high-speed rietwork archirecrure. Isochroners swirch rouies over time. Frames follow enabled routes withour slopping or intermediate nodes for frame header processing. The absence of such processing in (he Isochroners archirecrure is core for the switch f lciency and multi-protocol support. The switch makes possible Qualiry of Service (QoS) negotiation while promoting flexible resource sharing. The modular design is scaleable in number of nodes and link speed. I t can potentially reach scores of gigabits per second using current electronic iechnology. The switch implementation is simple and uses only ofl-(he-shelf componenrs. The switch interface provides novel services such QoS negotiation, mulri-prorocol frame forwarding, and synchronous service support for periphery protocol stacks. High-speed Networks (HSNs) place unprecedented challenges in a candidate switching technology. Switches have to be efficient both in terms of internal latency and throughput. Link throughput is rapidly evolving towards hundreds of gigabits per second or even scores of terabits per second. In such scenario, intemal latency must be of a few nanoseconds. Besides being efficicnt, an adequatc switching mechanism for HSNs must maximize bandwidth use while guaranteeing the necessary Quality of Service (QoS) that integrated data voice, and video applications need. This paper describes the design and implementation of a switch using the Isochronets architecture [4] that embodies a solution for these challenges. Current switching techniques. Packet Switching (PS) and Circuit Switching (CS) [I], may not appropriately satisfy these goals. For example, PS has limited support for guaranteed QoS, while CS enables limited bandwidth sharing. The reminder of this section introduccs thc main challenges in designing and implementing a HSN switch. Swiiching efficiency. Currcnt switching techniques rely on the fact that processing efficiency significantly prevails msmission effcicncy. Unfortunately, the scenario is likely to change when HSN link speeds reach hundreds of gigabits or even terabits per second. It may become difficult to process frame headers or synchronize sources and destinations at these speeds. QoS guaranrees. HSN switches must be able to support a variety of QoS needs in terms of maximum endend delay, jitter. loss, and bandwidth allocation. These parameters must be tunable by sources. Scalabifiry in speed. Link spceds have been increasing very rapidly in recent years and are expected to continue the trend with advances in optical transmissions. It is thus advisable not to base the switch design on peculiarity of specific muismission rates. Scalability in fhe nirmber olporrs. Scalability in the number of ports has always been an issue in switch design. Network systems are continuously growing and switches must be scaled accordingly. Implementation complexip and cosr. The provision of multimedia services to a large market will significantly increase the complexity and size of HSNs. If switches are complex, their maintenance and cost will affect the number of end users supported and cost of services provided. It is thus desirable to employ simple components (including switches) in the network. Inrefluce complexity and cosr. The engineering of the switch must not complicate the engineering of its interface. The simpler the interiacc. the more services can be directly connected to the switch at cheap cost. Additionally, current services may be easier 10 incorporate if thc inicrface is kept simple. Compatibility wirh citrrerir network devices. Current network devices will not cease to exist in future integrated HSNs. Slower speed technology will coexist with highs-speed technology, especially during transition phases. The switching technology must be compatible with existing devices to assure wide acceptance. Resource mitlriplexirtg. HSN must be able to multiplex resources when QoS can be traded for cheaper services. Minimal re-coiifigururio,i overhead. Switch re-confiiation must be performed without disturbing on-going The Isochronct switch developed in this work incorporates these features. This fact makes it a powerful solution for hightransmissions. speed switching systems.","PeriodicalId":174670,"journal":{"name":"Third IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPCS.1995.662032","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper overviews rhe elecrronic design and implementation of a switch based on the Isochronets high-speed rietwork archirecrure. Isochroners swirch rouies over time. Frames follow enabled routes withour slopping or intermediate nodes for frame header processing. The absence of such processing in (he Isochroners archirecrure is core for the switch f lciency and multi-protocol support. The switch makes possible Qualiry of Service (QoS) negotiation while promoting flexible resource sharing. The modular design is scaleable in number of nodes and link speed. I t can potentially reach scores of gigabits per second using current electronic iechnology. The switch implementation is simple and uses only ofl-(he-shelf componenrs. The switch interface provides novel services such QoS negotiation, mulri-prorocol frame forwarding, and synchronous service support for periphery protocol stacks. High-speed Networks (HSNs) place unprecedented challenges in a candidate switching technology. Switches have to be efficient both in terms of internal latency and throughput. Link throughput is rapidly evolving towards hundreds of gigabits per second or even scores of terabits per second. In such scenario, intemal latency must be of a few nanoseconds. Besides being efficicnt, an adequatc switching mechanism for HSNs must maximize bandwidth use while guaranteeing the necessary Quality of Service (QoS) that integrated data voice, and video applications need. This paper describes the design and implementation of a switch using the Isochronets architecture [4] that embodies a solution for these challenges. Current switching techniques. Packet Switching (PS) and Circuit Switching (CS) [I], may not appropriately satisfy these goals. For example, PS has limited support for guaranteed QoS, while CS enables limited bandwidth sharing. The reminder of this section introduccs thc main challenges in designing and implementing a HSN switch. Swiiching efficiency. Currcnt switching techniques rely on the fact that processing efficiency significantly prevails msmission effcicncy. Unfortunately, the scenario is likely to change when HSN link speeds reach hundreds of gigabits or even terabits per second. It may become difficult to process frame headers or synchronize sources and destinations at these speeds. QoS guaranrees. HSN switches must be able to support a variety of QoS needs in terms of maximum endend delay, jitter. loss, and bandwidth allocation. These parameters must be tunable by sources. Scalabifiry in speed. Link spceds have been increasing very rapidly in recent years and are expected to continue the trend with advances in optical transmissions. It is thus advisable not to base the switch design on peculiarity of specific muismission rates. Scalability in fhe nirmber olporrs. Scalability in the number of ports has always been an issue in switch design. Network systems are continuously growing and switches must be scaled accordingly. Implementation complexip and cosr. The provision of multimedia services to a large market will significantly increase the complexity and size of HSNs. If switches are complex, their maintenance and cost will affect the number of end users supported and cost of services provided. It is thus desirable to employ simple components (including switches) in the network. Inrefluce complexity and cosr. The engineering of the switch must not complicate the engineering of its interface. The simpler the interiacc. the more services can be directly connected to the switch at cheap cost. Additionally, current services may be easier 10 incorporate if thc inicrface is kept simple. Compatibility wirh citrrerir network devices. Current network devices will not cease to exist in future integrated HSNs. Slower speed technology will coexist with highs-speed technology, especially during transition phases. The switching technology must be compatible with existing devices to assure wide acceptance. Resource mitlriplexirtg. HSN must be able to multiplex resources when QoS can be traded for cheaper services. Minimal re-coiifigururio,i overhead. Switch re-confiiation must be performed without disturbing on-going The Isochronct switch developed in this work incorporates these features. This fact makes it a powerful solution for hightransmissions. speed switching systems.