The Multi-Protocol Gigabit-Per-Second Isochronet Switch Design And Implementation

D. Florissi, Y. Yemini
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The switch interface provides novel services such QoS negotiation, mulri-prorocol frame forwarding, and synchronous service support for periphery protocol stacks. High-speed Networks (HSNs) place unprecedented challenges in a candidate switching technology. Switches have to be efficient both in terms of internal latency and throughput. Link throughput is rapidly evolving towards hundreds of gigabits per second or even scores of terabits per second. In such scenario, intemal latency must be of a few nanoseconds. Besides being efficicnt, an adequatc switching mechanism for HSNs must maximize bandwidth use while guaranteeing the necessary Quality of Service (QoS) that integrated data voice, and video applications need. This paper describes the design and implementation of a switch using the Isochronets architecture [4] that embodies a solution for these challenges. Current switching techniques. Packet Switching (PS) and Circuit Switching (CS) [I], may not appropriately satisfy these goals. For example, PS has limited support for guaranteed QoS, while CS enables limited bandwidth sharing. The reminder of this section introduccs thc main challenges in designing and implementing a HSN switch. Swiiching efficiency. Currcnt switching techniques rely on the fact that processing efficiency significantly prevails msmission effcicncy. Unfortunately, the scenario is likely to change when HSN link speeds reach hundreds of gigabits or even terabits per second. It may become difficult to process frame headers or synchronize sources and destinations at these speeds. QoS guaranrees. HSN switches must be able to support a variety of QoS needs in terms of maximum endend delay, jitter. loss, and bandwidth allocation. These parameters must be tunable by sources. Scalabifiry in speed. Link spceds have been increasing very rapidly in recent years and are expected to continue the trend with advances in optical transmissions. It is thus advisable not to base the switch design on peculiarity of specific muismission rates. Scalability in fhe nirmber olporrs. Scalability in the number of ports has always been an issue in switch design. Network systems are continuously growing and switches must be scaled accordingly. Implementation complexip and cosr. The provision of multimedia services to a large market will significantly increase the complexity and size of HSNs. If switches are complex, their maintenance and cost will affect the number of end users supported and cost of services provided. It is thus desirable to employ simple components (including switches) in the network. Inrefluce complexity and cosr. The engineering of the switch must not complicate the engineering of its interface. The simpler the interiacc. the more services can be directly connected to the switch at cheap cost. Additionally, current services may be easier 10 incorporate if thc inicrface is kept simple. Compatibility wirh citrrerir network devices. Current network devices will not cease to exist in future integrated HSNs. Slower speed technology will coexist with highs-speed technology, especially during transition phases. The switching technology must be compatible with existing devices to assure wide acceptance. Resource mitlriplexirtg. HSN must be able to multiplex resources when QoS can be traded for cheaper services. Minimal re-coiifigururio,i overhead. Switch re-confiiation must be performed without disturbing on-going The Isochronct switch developed in this work incorporates these features. This fact makes it a powerful solution for hightransmissions. speed switching systems.","PeriodicalId":174670,"journal":{"name":"Third IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPCS.1995.662032","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

This paper overviews rhe elecrronic design and implementation of a switch based on the Isochronets high-speed rietwork archirecrure. Isochroners swirch rouies over time. Frames follow enabled routes withour slopping or intermediate nodes for frame header processing. The absence of such processing in (he Isochroners archirecrure is core for the switch f lciency and multi-protocol support. The switch makes possible Qualiry of Service (QoS) negotiation while promoting flexible resource sharing. The modular design is scaleable in number of nodes and link speed. I t can potentially reach scores of gigabits per second using current electronic iechnology. The switch implementation is simple and uses only ofl-(he-shelf componenrs. The switch interface provides novel services such QoS negotiation, mulri-prorocol frame forwarding, and synchronous service support for periphery protocol stacks. High-speed Networks (HSNs) place unprecedented challenges in a candidate switching technology. Switches have to be efficient both in terms of internal latency and throughput. Link throughput is rapidly evolving towards hundreds of gigabits per second or even scores of terabits per second. In such scenario, intemal latency must be of a few nanoseconds. Besides being efficicnt, an adequatc switching mechanism for HSNs must maximize bandwidth use while guaranteeing the necessary Quality of Service (QoS) that integrated data voice, and video applications need. This paper describes the design and implementation of a switch using the Isochronets architecture [4] that embodies a solution for these challenges. Current switching techniques. Packet Switching (PS) and Circuit Switching (CS) [I], may not appropriately satisfy these goals. For example, PS has limited support for guaranteed QoS, while CS enables limited bandwidth sharing. The reminder of this section introduccs thc main challenges in designing and implementing a HSN switch. Swiiching efficiency. Currcnt switching techniques rely on the fact that processing efficiency significantly prevails msmission effcicncy. Unfortunately, the scenario is likely to change when HSN link speeds reach hundreds of gigabits or even terabits per second. It may become difficult to process frame headers or synchronize sources and destinations at these speeds. QoS guaranrees. HSN switches must be able to support a variety of QoS needs in terms of maximum endend delay, jitter. loss, and bandwidth allocation. These parameters must be tunable by sources. Scalabifiry in speed. Link spceds have been increasing very rapidly in recent years and are expected to continue the trend with advances in optical transmissions. It is thus advisable not to base the switch design on peculiarity of specific muismission rates. Scalability in fhe nirmber olporrs. Scalability in the number of ports has always been an issue in switch design. Network systems are continuously growing and switches must be scaled accordingly. Implementation complexip and cosr. The provision of multimedia services to a large market will significantly increase the complexity and size of HSNs. If switches are complex, their maintenance and cost will affect the number of end users supported and cost of services provided. It is thus desirable to employ simple components (including switches) in the network. Inrefluce complexity and cosr. The engineering of the switch must not complicate the engineering of its interface. The simpler the interiacc. the more services can be directly connected to the switch at cheap cost. Additionally, current services may be easier 10 incorporate if thc inicrface is kept simple. Compatibility wirh citrrerir network devices. Current network devices will not cease to exist in future integrated HSNs. Slower speed technology will coexist with highs-speed technology, especially during transition phases. The switching technology must be compatible with existing devices to assure wide acceptance. Resource mitlriplexirtg. HSN must be able to multiplex resources when QoS can be traded for cheaper services. Minimal re-coiifigururio,i overhead. Switch re-confiiation must be performed without disturbing on-going The Isochronct switch developed in this work incorporates these features. This fact makes it a powerful solution for hightransmissions. speed switching systems.
多协议千兆位/秒等时交换机的设计与实现
本文概述了一种基于Isochronets高速网络架构的交换机的电子设计与实现。等时器会随时间切换路线。帧遵循启用的路由,不带坡或中间节点进行帧报头处理。在Isochroners架构中没有这种处理是交换机效率和多协议支持的核心。该交换机使服务质量(QoS)协商成为可能,同时促进了灵活的资源共享。模块化设计在节点数量和链路速度上具有可扩展性。使用目前的电子技术,它可能达到每秒几十千兆比特。交换机的实现很简单,只使用现成的组件。交换机接口提供了新的服务,如QoS协商、多协议帧转发和对外围协议栈的同步服务支持。高速网络对候选交换技术提出了前所未有的挑战。交换机必须在内部延迟和吞吐量方面都是高效的。链路吞吐量正迅速向每秒数百千兆比特甚至每秒数十太比特发展。在这种情况下,内部延迟必须是几纳秒。除了效率之外,一个适合hsn的交换机制必须最大限度地利用带宽,同时保证集成数据、语音和视频应用所需的QoS (Quality of Service,服务质量)。本文描述了使用Isochronets架构[4]的交换机的设计和实现,该架构体现了这些挑战的解决方案。当前的开关技术。分组交换(PS)和电路交换(CS) [I]可能不能适当地满足这些目标。例如,PS对保证QoS的支持有限,而CS支持有限的带宽共享。本节的提醒介绍了设计和实现HSN交换机的主要挑战。Swiiching效率。当前的交换技术依赖于处理效率显著高于传输效率这一事实。不幸的是,当HSN链路速度达到每秒数百千兆甚至太比特时,情况可能会发生变化。在这样的速度下,处理帧报头或同步源和目标可能会变得困难。QoS guaranrees。HSN交换机必须能够在最大端延迟、抖动方面支持各种QoS需求。损耗和带宽分配。这些参数必须根据源进行调整。速度上的可扩展性。近年来,链路速度一直在快速增长,随着光传输的进步,预计这一趋势将继续下去。因此,建议不要将开关设计建立在特定频率的特殊性上。成员表的可伸缩性。端口数量的可扩展性一直是交换机设计中的一个问题。网络系统不断增长,交换机必须相应地进行扩展。实现的复杂性和成本。向大型市场提供多媒体服务,会大大增加高速网络的复杂性和规模。如果交换机很复杂,其维护和成本将影响支持的最终用户数量和提供的服务成本。因此,在网络中使用简单的组件(包括交换机)是可取的。影响复杂性和成本。交换机的工程不能使其接口工程复杂化。界面越简单。更多的业务可以以低廉的成本直接连接到交换机上。此外,如果界面保持简单,当前的服务可能更容易合并。与citrrerir网络设备的兼容性。在未来的综合hsn中,现有的网络设备不会消失。低速技术将与高速技术共存,特别是在过渡阶段。交换技术必须与现有设备兼容,以确保广泛接受。资源mitlriplexirtg。当可以用QoS换取更便宜的服务时,HSN必须能够复用资源。最小的重新配置,i开销。开关重新确认必须在不干扰正在进行的情况下进行。在这项工作中开发的等时同步开关包含这些功能。这一事实使它成为高速变速器的强大解决方案。快速切换系统。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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