Runtime Estimation Model Based Graph Partitioning for Parallel Custom Instruction Selection

Abstract

Custom instruction selection is one of the most com- putationally difficult problems involved in the custom instruction identification for application-specific instruction-set processors. Most of existing research try to solve the custom instruction selection problem using sequential algorithms on a single compute node. Considering the high complexity of the problem, this paper proposes an efficient parallel method based on multi-depth graph partitioning for selecting custom instruction. Experimental result- s show that the proposed parallel custom instruction selection method outperforms two of the latest parallel methods and can achieve near-linear speedup.