Ravi Kumar, R. Nagulapalli, Rushikesh Hake, S. Vishvakarma
{"title":"A Low-Power 2-to-7 Modulus Programmable Prescaler with 50% Output Duty Cycle","authors":"Ravi Kumar, R. Nagulapalli, Rushikesh Hake, S. Vishvakarma","doi":"10.1109/ICECET55527.2022.9873078","DOIUrl":null,"url":null,"abstract":"This paper presents a novel optimized low-power multi-modulus programmable frequency divider with a modulus range of 2-to-7 with 50% output duty cycle for high-speed applications. The proposed divider is demonstrated with the division range from 2-127, which can be extended by adding more stages of the 2/3 Prescaler in the divider chain. The whole design is implemented using $0.18- \\mu \\mathrm{m}$ CMOS process with a supply of 1.8 V. From simulations result, the proposed design achieves a maximum operating frequency of 5 GHz with 6.5 mW of power consumption in divide-by-127 mode of operation while providing the 50% output duty cycle.","PeriodicalId":249012,"journal":{"name":"2022 International Conference on Electrical, Computer and Energy Technologies (ICECET)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Conference on Electrical, Computer and Energy Technologies (ICECET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECET55527.2022.9873078","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a novel optimized low-power multi-modulus programmable frequency divider with a modulus range of 2-to-7 with 50% output duty cycle for high-speed applications. The proposed divider is demonstrated with the division range from 2-127, which can be extended by adding more stages of the 2/3 Prescaler in the divider chain. The whole design is implemented using $0.18- \mu \mathrm{m}$ CMOS process with a supply of 1.8 V. From simulations result, the proposed design achieves a maximum operating frequency of 5 GHz with 6.5 mW of power consumption in divide-by-127 mode of operation while providing the 50% output duty cycle.