Power efficient all-digital delta-sigma TDC with differential gated delay line time integrator

Abstract

This paper presents a low-power all-digital first-order single-bit delta-sigma time-to-digital converter (TDC) with a differential bi-directional gated delay line time integrator. The differential time integrator features low power consumption accredited to the use of only one bi-directional gated delay line in performing time integration, full compatibility with technology scaling, rapid time integration, and inherently digitized output. Differential time integration is obtained by employing a time bolun mapping a single-ended time variable to be integrated to a pair of differential time variable with an embedded constant time offset that satisfying minimum gating width constraint. The TDC was designed in an IBM 130 nm 1.2 V CMOS technology. A sinusoidal time input of 333 ps amplitude and 244 kHz frequency generated using a differential voltage-to-time converter (VTC) clocked at 33 MHz is digitized by the TDC. The TDC was analyzed using Spectre from Cadence Design Systems with BSIM4 device model. Simulation results demonstrate the TDC provides a SFDR of 41.8 dB, a SNDR of 37.7 dB, and a time resolution of 5.3 ps over frequency rang 109–488 kHz while consuming 0.9 mW.