Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness

Abstract

A novel ESD implantation method is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness of CMOS integrated circuits in sub-quarter-micron CMOS processes. By using this method, the ESD current is discharged far away from the surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress. The MM ESD robustness of the gate-grounded NMOS (ggNMOS) with a device dimension of W/L= 300 /spl mu/m/0.5 /spl mu/m has been successfully improved from the original 450 V to become 675 V in a 0.25 /spl mu/m CMOS process.