FPGA implementation of improved binarizer design for context-based adaptive binary arithmetic coder

Abstract

New and modern video encoders employ the CABAC (Context-Based Adaptive Binary Arithmetic Coding) to allow a high compression and/or improved video quality. CABAC is composed of three main blocks which are binarizer, context modeler and binary arithmetic coder block. Since the binarizer block is used in the beginning of the encoder process, the whole performance of CABAC depends a lot on the design of the binarizer. In this paper, we propose an efficient implementation of this block. The novelty of the proposed design with respect to existing ones is that it takes advantages of new entropy coding's characteristics. The strength of the propose binarizer is that it allows the binarization with the seven methods indicated in the coding standard. Moreover, the proposed design can be integrated into CABAC module of the encoder to generate the bins of the Syntax Elements (SE). One uniquely interesting feature of the proposed design is that it could be configured for multi-standard (HEVC/H264) scenario. The proposed architecture is found to offer many advantages in terms of hardware complexity, regularity and modularity. Experimental results obtained from Xilinx Spartan 6 FPGA implementation show the advantage of the proposed method. More particularly, the proposed architecture consumes about 376 slices and able to process at 287 MHz.