Analogue current quantizer architectures for implementing integer division-like functions

N. Petrellis, M. Birbas, J. Kikidis, A. Birbas
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引用次数: 6

Abstract

An analogue current quantization circuit that can implement the integer division by a constant number, the integer floor function, and a function generator with a parametric ladder-like output is presented in this paper. These functions can be exploited in Analogue-to-Digital Converters (ADCs), fuzzy logic and neural networks as well as in signal processing units. Various architecture alternatives are presented which achieve different integer division resolution ranging from 1:2 to 1:65536 or more. High speed and low voltage supply are achieved in ADCs that are based on this divider due to the usage of current mode techniques. Nevertheless, the most important advantages of the presented architectures are the very low power consumption and die area that they require.
模拟实现整数除法功能的电流量化器架构
本文设计了一种模拟电流量化电路,可实现整数除常数、整数底函数和具有参数梯形输出的函数发生器。这些功能可用于模数转换器(adc)、模糊逻辑和神经网络以及信号处理单元。提出了各种架构方案,以实现从1:2到1:65536或更高的不同整数除法分辨率。由于使用电流模式技术,基于该分压器的adc实现了高速和低电压供电。然而,所提出的架构最重要的优点是非常低的功耗和所需的芯片面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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