Implementation of MAC using area efficient and reduced delay vedic multiplier targeted at FPGA architectures

Abstract

The Multiply-Accumulator (MAC) unit always lies in the critical path that determines the speed of the overall hardware systems. Therefore, a high-speed MAC that is capable of supporting multiple precisions and parallel operations is highly desirable. This paper describes the implementation of a MAC unit using area efficient Vedic multiplier which enhanced in terms of area and path delay. Speed of the multiplier is very important to any Digital Signal Processors (DSPs). To construct a N×N bit Vedic Multiplier, four N/2×N/2 VM and three N-bit Ripple Carry Adders (RCAs) are required. But in our proposed VM, instead of 3 N-bit RCA, only one N-bit RCA and our two proposed adders are used. In our proposed Adders, the area required for N-bit RCA has been reduced, leading to a greater reduction in the logic delay. We have developed the generalized architectures for NxN VM, MAC unit and for our proposed Adders. The proposed MAC and conventional MAC are coded in Verilog, synthesized and simulated using ISE simulator. It is implemented on the Xilinx Spartan6 family xc6slx150t-4fgg900 FPGA. The Area and logic delay of the proposed MAC and conventional VM are compared.