An optimized SIMD implementation of the HEVC/H.265 video decoder

Abstract

This paper focuses on the optimization process of the HEVC/H.265 video decoder on suitable architectures for mobile devices. The solutions developed to support the new HEVC/H.265 features are shown together with the achieved performance. The HEVC/H.265 decoder complexity has been evaluated and the most demanding modules have been optimized with Single Instruction Multiple Data (SIMD) instructions. Even though the here described approach has a general meaning, the effectiveness of the proposed solutions has been demonstrated on ARM architecture. In particular, we have selected the Cortex A9 processor with NEON SIMD extension. We will demonstrate that the resulting HEVC/H.265 application can decode in real-time 720p (1280×720) streams at 30 frames per second on a single core ARMv7 at 1.2 GHz.