A design for-testability technique for shorts and bridging faults in BiCMOS logic families

Abstract

The paper provides the results of a simulation-based fault characterization study of BiCMOS logic families. The author shows that most of the shorts cause I/sub DDQ/ faults, while open defects result in delay or stuck-open faults. The author proposes a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.