Mapping schemes of image recognition tasks onto highly parallel SIMD/MIMD processors

Abstract

Smart camera applications based on image recognition techniques require significant levels of computation and must operate within limited power budgets. This paper focuses on the schemes of mapping image recognition tasks onto a series of low-power highly parallel SIMD/MIMD mode switching processors called IMAPCAR2. In this paper, we discuss hardware design considerations, the schemes of mapping image tasks onto the architecture using the SIMD or MIMD execution modes, and the way to choose between execution modes. Benchmark results show that the measured performance of an IMAPCAR2-300 (108 MHz, 128 PE / 32 PU, 90-nm, ≪ 1 W) processor running the compiler-generated code of programs based on the proposed mapping schemes is up to 27 times faster using the SIMD mode, or up to 2.8 times faster using the MP mode than a 1.6GHz general purpose processor that consumes a similar amount of power.