A high linearity analog front end for multiprocessor SOC integration

Abstract

This paper reports a high linearity low power analog front end (AFE) subsystem composed of a contact image sensor (CIS) input amplifier, a programmable gain amplifier (PGA), a 10-bit pipelined analog-to-digital converter (ADC) and a 10-bit offset calibration digital-to-analog converter (DAC). The AFE was integrated into a mixed-signal multiprocessor system-on-chip (SOC) by using conventional ASIC flow. This SOC is fabricated in 0.14 /spl mu/m CMOS process with 3.3 V/1.5 V power supplies. The AFE runs up to 20 Ms/s sampling rate, ATE measurement shows on-chip performance of /spl plusmn/0.8LSB DNL and /spl plusmn/0.9LSB INL with less than 38 mW power dissipation. Timing, functional and behavior models are developed to support ASIC design flow and tools.