A Low-Power 25GS/Sec Sample and Hold Circuit with Active-Load Inductors

Abstract

This work presents a novel design of a sample and hold circuit which operates at 25GS/s. The circuit consists of three main stages. The first stage is the input buffer which provides a high frequency boost using an active-load inductor instead of the commonly used passive inductor. The second stage is the switch stage which is responsible for sampling the input signal with high linearity. Finally, the output buffer is used to recover the high frequency component of the signal. The circuit is designed in 28nm CMOS technology used in digital circuits and uses a 1V supply. It is simulated using a 3GHz input signal that has a differential peak to peak voltage amplitude of 0.4V and a 25GHz sampling clock signal. The proposed circuit consumes a total power of 2.47mW and occupies an area of 0.005mm2. The achieved Effective Number Of Bits (ENOB) is 5 bits and the Total Harmonic Distortion, THD, is −40dB. The sampled signal has a droop rate of 0.35mV/psec.