A 2-Stage Phase Interpolator Used in Clock Data Recovery Circuit

Abstract

Phase interpolation based digital clock data recovery are widely adopted in Serdes design because of capability of dealing with burst mode. In this paper, a two-stage phase interpolator utilizing IQ clock are proposed. The tail current in first stage can be trimmed to equalized the amplitude difference caused by first stage interpolation. The second stage operates 8-step phase interpolation by using clock with 45° difference. The Circuit is implemented in HLMC 55nmdr process. The DNL is 0.8LSB, INL is 2LSB, typical power consumption is 36.36mW@1.2V. PI operating frequency is 2.5G and its control logic operates at 312.5MHz.