Efficient implementation techniques for vector memory systems

T. Chiueh, Manish Verma, Sanjay A. Padubidri
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引用次数: 1

Abstract

Existing vector machines' memory systems use heavy interleaving and SRAM technology for faster data access. In this paper, we present an efficient vector memory architecture that adopts prime-degree memory interleaving and exploits the capabilities of new-generation DRAM chips with small SRAM cache. The major contribution of this paper is an incremental indexing scheme for prime-degree memory interleaving that takes at most two integer divisions as the initial start-up overhead for each logical vector memory access, and generates one bank/offset address pair per cycle thereafter. We have also developed a vector pre-fetching scheme that ensures that vector data elements are in the SRAM buffers before they are accessed, thus effectively masking the long delays associated with normal DRAM accesses.<>
矢量存储系统的有效实现技术
现有矢量机的存储系统使用大量交错和SRAM技术来实现更快的数据访问。在本文中,我们提出了一种高效的矢量存储器架构,该架构采用质数存储器交错,并利用具有小SRAM缓存的新一代DRAM芯片的功能。本文的主要贡献是一种质数度存储器交错的增量索引方案,该方案对每个逻辑向量存储器访问最多使用两个整数除法作为初始启动开销,并在此后的每个周期中生成一个银行/偏移地址对。我们还开发了一种矢量预取方案,确保矢量数据元素在被访问之前位于SRAM缓冲区中,从而有效地掩盖了与正常DRAM访问相关的长时间延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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