Design and Analysis of High Performance Multiplier Circuit

I. Hussain, C. Pandey, S. Chaudhury
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引用次数: 11

Abstract

Multiplier is of the most important blocks of many VLSI application. So, it is required to design high performance multiplier to boost up the performance of those circuits and systems. In this work, a high performing Multiplier has been designed by using Wallace tree algorithm. The multiplier has been designed in three modules. Initially partial products are generated followed by partial products processing. Finally, final addition is computed in the 3rd module. Partial products have been generated by using AND gates. Partial products are computed by using Wallace tree logarithm. Final addition has been done by fast adder. The performance of the proposed multiplier circuit is evaluated by using 90nm CMOS technology at the Synopsys tool. The performance of the same is compared conventional multiplier circuits. The performance of the proposed adder has been found to be satisfactory.
高性能乘法器电路的设计与分析
乘法器是许多VLSI应用中最重要的模块之一。因此,需要设计高性能的乘法器来提高这些电路和系统的性能。本文采用Wallace树算法设计了一种高性能的乘法器。该乘法器设计分为三个模块。首先生成部分产品,然后对部分产品进行加工。最后,在第三个模块中计算最终的加法。部分产品已使用与门产生。用华莱士树对数计算部分积。最后的加法是由快速加法器完成的。在Synopsys工具上使用90nm CMOS技术对所提出的乘法器电路的性能进行了评估。对传统乘法器电路的性能进行了比较。该加法器的性能令人满意。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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