Variable taper CMOS buffer design

Abstract

A variable taper (VT) approach is proposed for the design of CMOS buffers. The minimum propagation delay obtained by using a VT buffer is approximately 12% higher than the minimum propagation delays obtained by using a conventional fixed taper (FT) approach. A modification to the initial stages of a VT buffer reduces this difference to within 2% of a FT buffer. For buffer designs with similar propagation delays, a VT buffer design usually takes significantly less silicon area and dissipates less power.<>