Design of floating point units for interval arithmetic

Abstract

In this paper, hardware units for interval addition, multiplication and divide-add fused are presented. Regarding interval addition, a new architecture of double path adder, is presented. This architecture exploits the parallel structure of double path adder. Regarding multiplication, the proposed architecture is based on a dual result multiplier (floating point multiplication unit with two differently rounded results for the same pair of operands) and two floating point comparators. The goal of the divide-add fused unit is to increase the performance of the interval Newton's method. Algorithm and architecture for this operation, inspired by the ones used for multiply-add fused, are proposed.