A 40nm CMOS single-ended switch-capacitor harmonic-rejection power amplifier for ZigBee applications

2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2016-05-22 DOI:10.1109/RFIC.2016.7508289

Chenxi Huang, Yongdong Chen, Tong Zhang, V. Sathe, J. Rudell

引用次数: 16

Abstract

This paper describes a single-ended switch-capacitor harmonic-rejection power amplifier to operate in the 915 MHz ISM band for ZigBee applications. A multipath feed-forward harmonic-rejection technique is employed to suppress the 2nd/3rd/4th harmonics of the switch-capacitor power amplifier (PA) by 48/17/24 dB, respectively. The measured PA peak drain efficiency is 43% at a peak output power of 8.9dBm with the harmonic-rejection enabled. This PA was implemented in a 40nm TSMC CMOS process with an active area of 180μm×700μm.

查看原文本刊更多论文

用于ZigBee应用的40nm CMOS单端开关电容谐波抑制功率放大器

本文介绍了一种用于ZigBee应用的915mhz ISM频段单端开关电容抗谐波功率放大器。采用多径前馈谐波抑制技术将开关电容功率放大器(PA)的第2 /3 /4次谐波分别抑制了48/17/24 dB。在峰值输出功率为8.9dBm并使能抑制谐波时，测量到的PA峰值漏极效率为43%。该PA在40nm TSMC CMOS工艺中实现，活性面积为180μm×700μm。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

自引率

0.00%

发文量